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| Name | Distributed Design Implementation |
| Video Uploader | Video From Semiconductor Engineering |
| Upload Date | This Video Uploaded At 04-12-2019 07:00:00 |
| Video Discription | PV Srinivas, group director for R&D at Synopsys, talks with Semiconductor Engineering about the impact of larger chips and increasing complexity on design productivity, why divide-and-conquer doesn’t work so well anymore, and how to reduce the number of blocks that need to be considered to achieve faster timing closure and quicker time to market. |
| Category | Science & Technology |
| Tags | Synopsys | Semiconductor Engineering | chiplets | synthesis | place and route | timing closure | multi-core processors | verification | design implementation |
