Hellow guys, Welcome to my website, and you are watching Physical Design Flow | PnR flow | RTL-to-GDSII flow | Back End Flow | Innovus tool flow. and this vIdeo is uploaded by Team VLSI at 2018-10-30T20:06:10-07:00. We are pramote this video only for entertainment and educational perpose only. So, I hop you like our website.
| Name | Physical Design Flow | PnR flow | RTL-to-GDSII flow | Back End Flow | Innovus tool flow |
| Video Uploader | Video From Team VLSI |
| Upload Date | This Video Uploaded At 31-10-2018 03:06:10 |
| Video Discription | This is the session-8 of RTL-to-GDSII flow series of video tutorial. In this session, we will see the flow of Place and route (PnR)stages in very interesting way. First we will see the requirements of PnR tools (Innovus), set of input and output files and then we will move to the flow. Physical design has various stages of design and lots of validation to after each stages. A basic flow has been semonstrated here. In this RTL-to-GDSII flow of video series, there are total 10 sessions. We have covered all the stages of ASIC design using EDA tools demonstration and also the basic theories. Part-wise descriptions of the different session and the link of videos are as follow. 1. Session-1: Overview of RTL to GDSII flow | Basic terms in the flow Video link: https://youtu.be/THXPuNNdPqw 2. Session-2: Flow in EDA tool's perspective | Different EDA tools | various files Video link: https://youtu.be/S4Yzexeq3l8 3. Session-3: Functional verification of RTL | using Synopsys VCS | VCS demo Video link: https://youtu.be/RDtGyHfP_eQ 4. Session-4: Logic Synthesis flow | RTL to gate-level netlist | Design compiler Video link: https://youtu.be/tLVAyfTfTNY 5. Session-5: Logic Synthesis | Design Compiler | Command-line | gate level netlist Video link: https://youtu.be/sIDe76QFG2g 6. Session-6: Logic Synthesis | Design Compiler | GUI Mode| design_vision Video link: https://youtu.be/N3CCQmcX3fk 7. Session-7: Logic Equivalence Check using Formality |S8| RTL-to-GDSII flow | Formality tutorial Video link: https://youtu.be/CFRqPnqifx0 8. Session-8: Physical Design Flow | PnR flow |RTL-to-GDSII flow | innovus flow Video link: https://youtu.be/1kLUdi0qNBo 9. Session-9: Design Import | Physical Design |RTL-to-GDSII flow | innovus tools tutorial Video link:https://youtu.be/OMhTtqnzDOA 10.Session-10: Place and Route in Cadence Innovus | full PnR flow | Cadence Innovus demo Video link: https://youtu.be/TDvq1hVXzRc ====Connect with us========================== All on one page: https://www.teamvlsi.com/p/contact_8.html Blog: https://www.teamvlsi.com Facebook Page: https://www.facebook.com/teamvlsi WhatsApp Group: https://chat.whatsapp.com/C6etLHR6oAf6G9bLGDwdOf Telegram Group: https://t.me/teamvlsi (Or search team VLSI on telegram) Email: teamvlsi2014@gmail.com ============================== #BackEndFlow #PnRFlow #InnovusFlow |
| Category | Education |
| Tags | Physical Design | Physical Design Flow | Physical Design flow in VLSI | PnR flow | PnR flow in innovus | Innovus tool flow | Cadence Innovus | Placemet and routign | clock tree synthesis | CTS | Static time analaysis | STA | RTL-to-GDSII flow | ASIC flow | IC Design flow | teamVLSI | team vlsi | rajeshyadav | rajeshyadav.ece49@gmail.com |
