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| Name | Packaging Part 6 - Wafer to Panel Level Packaging |
| Video Uploader | Video From Navid Asadi |
| Upload Date | This Video Uploaded At 10-02-2021 12:24:46 |
| Video Discription | References: [1] Gotro, J. (2018, March 18). Polymers in electronic packaging: Introduction to fan-out wafer level packaging. Retrieved March 01, 2021, from https://polymerinnovationblog.com/polymers-in-electronic-packaging-introduction-to-fan-out-wafer-level-packaging/ [2] Panel level packaging. (n.d.). Retrieved March 01, 2021, from https://www.ulvac.co.jp/special/en/plp/ [3] G erven, P. (2017, January 19). Euv for dummies. Retrieved March 01, 2021, from https://bits-chips.nl/artikel/euv for-dummies/ [4] Fraunhofer IZM, Volker Mai, Fan-out wafer- panel level packaging. (2019, February 07). Retrieved March 01, 2021, from https://www.izm.fraunhofer.de/en/abteilungen/system_integrationinterconnectiontechnologies/arbeitsgebiete/fan-out-wafer-level-packaging.html [5] LAPEDUS, M. (2019, March 03). Fan-out wars begin. Retrieved March 01, 2021, from https://semiengineering.com/fan-out-wars-begin/ [6] Kumar, Aditya & Dingwei, Xia & Sekhar, Vasarla & Lim, Sharon & Keng, Chin & Sharma, Gaurav & Vempati, S.R. & Kripesh, Vaidyanathan & Lau, John & Kwong, Dim-Lee. (2009). Wafer Level Embedding Technology for 3D Wafer Level Embedded Package. Proceedings - Electronic Components and Technology Conference. 1289 - 1296. 10.1109/ECTC.2009.5074177. [7] Braun, T., Becker, K.-F., Hoelck, O., Voges, S., Kahle, R., Dreissigacker, M., & Schneider-Ramelow, M. (2019). Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration. Micromachines, 10(5), 342. MDPI AG. Retrieved from http://dx.doi.org/10.3390/mi10050342 [8] Happich, J. (2015, June 26). Wafer-level packaging is not enough, SAY OSATS. Retrieved March 01, 2021, from https://www.eenewseurope.com/news/wafer-level-packaging-not-enough-say-osats/page/0/1 [9] Fan, X. (2010). Wafer level packaging (WLP): Fan-in, fan-out and three-dimensional integration. 2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE), 1-7. [10] Yuan, J., Jeung, W., Lim, C., Park, S., Kweon, Y., & Yi, S. (2008). A low-cost through via interconnection for ISM WLP. Microsystem Technologies, 15, 1273-1277. [11] Verizon Wireless Motorola RAZR V3m - Silver. (n.d.). Retrieved March 1, 2021, from https://www.amazon.com/Verizon-Wireless-Motorola-RAZR-V3m/dp/B002UHS0UI [12] IPhone 5s - Technical Specifications. (n.d.). Retrieved March 01, 2021, from https://support.apple.com/kb/sp685?locale=en_US [13] Fraunhofer IZM, Volker Mai, Fan-out wafer- panel level packaging. (2019, February 07). Retrieved March 01, 2021, from https://www.izm.fraunhofer.de/en/abteilungen/system_integrationinterconnectiontechnologies/arbeitsgebiete/fan-out-wafer-level-packaging.html [14] Lee, C., Bondur, T., & Ranjan, M. (2017, April 3). Technology and economic considerations for panel-level fan-out packaging. Retrieved March 01, 2021, from https://blog.lamresearch.com/technology-and-economic-considerations-for-panel-level-fan-out-packaging/ [15] T. Braun et al., "Panel Level Packaging - A View Along the Process Chain," 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2018, pp. 70-78, doi: 10.1109/ECTC.2018.00019. [16] Fraunhofer IZM, Volker Mai, Fan-out wafer- panel level packaging. (2019, February 07). Retrieved March 01, 2021, from https://www.izm.fraunhofer.de/en/abteilungen/system_integrationinterconnectiontechnologies/arbeitsgebiete/fan-out-wafer-level-packaging.html [17] Braun, T. Fraunhofer IZM (2015). Opportunities and Challenges for Fan-out Panel Level Packaging (FOPLP). In SiP Global Summit. Taipei, Taiwan. Retrieved from https://docplayer.net/20781291-Opportunities-and-challenges-for-fan-out-panel-level-packaging-foplp.html. |
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